Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a substrate or wafer. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
The geometry of structures fabricated on a semiconductor wafer depends on process conditions during lithographic exposure. Process parameters such as focus, dose, and scanner aberration affect the shape of the resulting structures differently, depending on the type of structure being fabricated. For example, relatively isolated structures are more sensitive to focus changes, while relatively dense structures are more sensitive to changes in dosage. Device functionality and manufacturing yield is limited by the quality of the structures formed by patterning steps, e.g., lithography, deposition, etch, etc.
The lateral dimensions of integrated circuit features (e.g., CD) are primarily limited to the resolution of the lithography tools involved in the fabrication process flow. Lithography and etch processes are continuously progressing toward smaller dimensions. Multiple patterning techniques are commonly employed to decrease lateral dimensions of integrated circuits. Today, advanced lithography tools operating at wavelengths of 193i nanometers employ multiple patterning techniques (e.g., double and triple patterning) to realize features having lateral dimensions of less than 20 nanometers. Lateral dimensions are expected to shrink further in upcoming fabrication technology nodes.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry, ellipsometry, and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, bandgap, composition, overlay and other parameters of nanoscale structures.
Existing model based metrology methods typically include a series of steps to model and then measure structure parameters. Typically, measurement data is collected (e.g., DOE spectra) from a particular metrology target. An accurate model of the optical system, dispersion parameters, and geometric features is formulated. Film spectra measurements are collected to determine material dispersions. A parametric geometric model of the target structure is created along with an optical model. In addition, simulation approximations (e.g., slabbing, Rigorous Coupled Wave Analysis (RCWA), etc.) must be carefully performed to avoid introducing excessively large errors. Discretization and RCWA parameters are defined. A series of simulations, analysis, and regressions are performed to refine the geometric model and determine which model parameters to float. A library of synthetic spectra is generated. Finally, measurements are performed using the library and the geometric model.
Optical metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield and optimize device performance. As design rules and process windows continue to shrink in size, characterization becomes more difficult. In addition, the increasing number of parameters required to characterize complex structures, leads to increasing parameter correlation. As a result, the parameters characterizing the target often cannot be reliably decoupled with available measurements.
Existing methods assume that the materials comprising a semiconductor structure under measurement are optically isotropic (i.e., material parameters are the same regardless of the azimuth angle, angle of incidence, electric field polarization, etc.). For small feature sizes, this results in significant subsystem mismatch, even for simple optical critical dimension (OCD) structures, poor spectral fit quality especially among combinations of different measurement settings, inaccurate geometric profiles, large disagreement with reference measurements (e.g., transmission electron microscopy (TEM), CD scanning electron microscopy (CDSEM), etc.), and lower medium contrast, and as a result, higher correlation among geometric parameters. These issues are described in greater detail in the article entitled, “Nanoscale optical critical dimension measurement of a contact hole using deep ultraviolet spectroscopic ellipsometry”, by H. Chouaib and Q. Zhou, published in J. Vac. Sci. Technol. B 31, 011803 (2013), the subject matter of which is incorporated herein by reference in its entirety.
In response to these challenges, more complex optical metrology tools have been developed. For example, tools with multiple angles of illumination, shorter illumination wavelengths, broader ranges of illumination wavelengths, and more complete information acquisition from reflected signals (e.g., measuring multiple Mueller matrix elements in addition to the more conventional reflectivity or ellipsometric signals) have been developed.
However, these approaches have not reliably overcome fundamental challenges associated with measurement of many advanced targets (e.g., complex 3D structures, structures smaller than 10 nm, structures employing opaque materials) and measurement applications (e.g., line edge roughness and line width roughness measurements).
Accordingly, it would be advantageous to develop high throughput systems and methods for characterizing structures and materials in the semiconductor manufacturing process. In particular, it would be advantageous to develop a robust, reliable, and stable approach to in-line metrology of semiconductor structures having small feature size (e.g., less than 20 nanometers).